The present invention relates to a synthesizer apparatus for generating a signal of an arbitrary frequency and, more particularly, to a synthesizer apparatus which can save power consumption.
A synthesizer apparatus is normally used in an oscillator of a tranceiver for performing multi-frequency radio communication. When such a tranceiver is used in a mobile radio communication service, the mobile supplies power. Therefore, the synthesizer apparatus used therefor must be of a low power consumption type.
FIG. 1 is a block diagram showing a conventional synthesizer apparatus taking a low power consumption requirement into consideration. FIGS. 2(a) to 2(g) are respectively waveforms of signals denoted by a to g in FIG. 1. A signal produced by a reference oscillator 1 is frequency-divided by a frequency divider 2, and is output as a signal a shown in FIG. 2(a). This signal is counted by a counter 6, and the counter 6 supplies a pulse signal b having a period three times an input pulse period to a set terminal S of an R-S flip-flop (to be referred to as an FF hereinafter) 9. As a result, the FF 9 is reset, and outputs a High level ("H") signal to a power supply 10. When the power supply 10 receives the "H" signal, it enables a frequency divider 8 for a predetermined period of time T, as shown in FIG. 2(g).
A voltage controlled oscillator (to be referred to as a VCO hereinafter) 5 continuously outputs a signal c shown in FIG. 2(c) to the frequency divider 8, and the frequency divider 8 frequency-divides the input signal only in the time T. A frequency-dividing constant of the frequency divider 8 is set to be 5. After a time T1 corresponding to a settling time of the frequency divider 8 has passed from the leading edge of the output signal b from the counter 6, the frequency divider 8 outputs, to a phase comparator 3, a signal d which goes to "H" in synchronism with the leading edge of the signal c supplied from the VCO 5.
A counter 7 receives the output signal a from the frequency divider 2, and produces a carry out signal e which goes to "H" in response to the leading edge of the (3n-1) pulse (n is a positive integer) of the signal a. The counter 7 supplies the signal e to the phase comparator 3. When the phase comparator 3 receives the "H" carry out signal from the counter 7, it detects a phase difference between the signal a supplied from the frequency divider 2 and the signal b supplied from the frequency divider 8, and outputs a signal f shown in FIG. 2(f). Since the signal f is supplied to the VCO 5 through a loop filter 4, the VCO 5 generates the signal c having a frequency for canceling the received signal to zero. Note that the carry out signal e is supplied to a reset terminal R of the FF 9 through an inverter 11.
In the circuit shown in FIG. 1, the frequency divider 8 must perform a high-speed operation, and consumes large power. However, if the frequency divider 8 is intermittently operated in response to a signal g as needed, low power consumption can be attained.
However, when the output frequency of the VCO 5 increases, and a time corresponding to one period is on the order equal to the settling time of the frequency divider 8, the frequency divider 8 often sends its output to be delayed by one period of the output frequency of the VCO 5 from the leading edge of the signal b in accordance with the rising condition of the power supply 10 and the rising temperature characteristic of the frequency divider 8, as indicated by symbol A in FIG. 2. For this reason, even if output signal intervals T2 of the frequency divider 8 are equal to each other, the output signals f from the phase comparator 3 have difference pulse widths, as shown in FIG. 2, and this interferes with synchronization of the VCO 5.